In this position, the individual will be responsible for developing and supporting physical verification rule decks (LVS/DRC/ERC) for layout group. The individual will also complete placement and routing flow/methodology development, develop/support/calibrate parasitic extraction flow for design groups, develop the CAD flow for memory design as per the layout and design requirements and improve overall productivity for layout group through various scripts and SKILL programming.
This position requires 0-2 years of experience in VLSI CAD Development and Support, solid programming experience in C, C++, Perl, good understanding of VLSI basics: CMOS integrated circuit and excellent written and verbal communication skills. Bilingual Japanese/English is required. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.